Referring to FIG. 1, a conventional dynamic random access memory cell 101 is shown. As shown, the memory cell comprises a cell transistor 110 and a cell capacitor 150. A first junction 111 of the transistor is coupled to the bitline 125, and a second junction 112 is coupled to the capacitor. A gate electrode 113 of the transistor is coupled to the wordline 126.
The capacitor comprises a first electrode 153 and a second electrode 157 separated by a dielectric layer 159. The first electrode 153 of the cell capacitor is coupled to the second junction of the transistor. The first electrode serves as a storage node for storing information and is typically referred to as a storage node electrode. The second electrode can be coupled to a constant voltage source 180 and is usually referred to as a plate electrode.
A plurality of cells is arranged in rows and columns to form a cell array, connected by wordlines in the row direction and bitlines in the column direction. The second or plate electrode of the cell capacitor typically serves as a common plate for the cells in the array.
The bitlines of the array are coupled to sense amplifiers to facilitate memory accesses. Each sense amplifier is coupled to a pair of bitlines. The bitline of the bitline pair containing the selected memory cell is referred to as the bitline true and the other is referred to as the bitline complement.
The memory cell is accessed by activating the wordline to render the transistor conductive, connecting the bitline to the storage node. For a read operation, information stored in the memory cell is passed through to the bitline. The charge from the memory cell produces a voltage differential on the bitline pair. The sense amplifier senses the differential voltage and amplifies it, producing a signal representing the information stored in the cell. In a write operation, the sense amplifier charges the bitline true to a voltage level that represents the information that is to be stored in the cell.
FIG. 2 is a timing diagram 201 showing the operation of a conventional memory cell. The plate electrode (PE), the bitline true (BL), the wordline (WL), and the storage node (SN) signals are shown. As shown, the plate electrode of the cell capacitor is connected to a constant voltage source V.sub.pe which, for example, is about V.sub.blh /2, where V.sub.blh is equal the bitline high level. For a write operation 270, BL is charged to a voltage level equal to the information that is to be written into the cell. Activating the wordline, as indicated by WL=V.sub.pp, connects the storage node to the bitline. After the data is written into the cell, the wordline is deactivated (e.g., WL=0) to isolate or float the storage node.
In preparation of a read operation 260 or a memory access, an equalization circuit equalizes the bitline pair to a voltage level of V.sub.bleq. V.sub.bleq, for example, is equal to about V.sub.blh /2. Other values such as V.sub.DD /2 are also useful. The wordline is activated to commence the read operation. Activating the wordline connects the storage node to the bitline. Depending on the value stored, the bitline is pulled high or low slightly to create a negative or positive differential voltage between on the bitline pair.
The read operation discharges the storage node to about V.sub.bleq. To restore the information back into the memory cell, a restore operation 290 is performed after the read operation.
As described, the conventional DRAM IC senses information stored in the storage node of a cell capacitor through the junction of the cell transistor. Such a memory cell sensing scheme requires a contact between the bitline and a junction of the cell transistor. This requirement makes it difficult for cell designs having a cell area of, for example, less than 6F.sup.2 (where F is the minimum feature size) to accommodate the bitline contact, especially if the cell capacitor is a stack capacitor.
As evidenced from the foregoing discussion, it is desirable to provide an improved sensing scheme that facilitates smaller cell sizes.